Technically Speaking, Inc.
Advanced VHDL | Onsite / Online Albuquerque NM
Course Description
Increase your VHDL proficiency by learning advanced techniques that will help you write more robust and reusable code. This comprehensive course is targeted toward designers who already have some experience with VHDL.
The course highlights modeling, testbenches, RTL/synthesizable design, and techniques aimed at creating parameterizable and reusable designs. The majority of class time is spent in challenging hands-on labs as compared to lecture modules.
Increase your VHDL proficiency by learning advanced techniques that will help you write more robust and reusable code. This comprehensive course is targeted toward designers who already have some experience with VHDL.
The course highlights modeling, testbenches, RTL/synthesizable design, and techniques aimed at creating parameterizable and reusable designs. The majority of class time is spent in challenging hands-on labs as compared to lecture modules.
Course Outline
Day 1
▪ Review of Current Knowledge
▪ Simulation Concepts
▪ Advanced Data Types
▪ Subprograms and Design Attributes
▪ Lab 1: Flexible Functions
▪ Access Type Techniques and Blocks
▪ Lab 2: Linked Lists with Access Types
▪ Utilizing File IO
▪ Lab 3: TextIO Techniques
Day 2
▪ Cool Stuff with VHDL
▪ Lab 4: Creating Real-World Simulations
▪ Supporting Multiple Platforms
▪ Lab 5: Supporting Multiple Platforms
▪ Non-Integer Numbers
▪ Point Numbers
Day 1
▪ Review of Current Knowledge
▪ Simulation Concepts
▪ Advanced Data Types
▪ Subprograms and Design Attributes
▪ Lab 1: Flexible Functions
▪ Access Type Techniques and Blocks
▪ Lab 2: Linked Lists with Access Types
▪ Utilizing File IO
▪ Lab 3: TextIO Techniques
Day 2
▪ Cool Stuff with VHDL
▪ Lab 4: Creating Real-World Simulations
▪ Supporting Multiple Platforms
▪ Lab 5: Supporting Multiple Platforms
▪ Non-Integer Numbers
▪ Point Numbers
▪ Course Summary
Lab Descriptions
▪ Lab 1: Flexible Functions – Construct and use predefined attributes to build functions and
procedures that automatically adjust to the size of the passed arguments as well as creating a
reusable module with unconstrained ports.
▪ Lab 2: Linked Lists with Access Types – Create linked lists to capture arbitrarily large data
sets. Also included in this lab is a reusable helper package for managing singly linked lists.
▪ Lab 3: TextIO Techniques – Load memory for synthesis via a text file using the TextIO extensions
for std_logic and std_logic_vector as provided by the std_logic_TextIO package.
▪ Lab 4: Creating Real-World Simulations – Create
spread-spectrum clocks with jitter and other real-world factors.
Model board and behavioral component delay.
▪ Lab 5: Supporting Multiple Platforms – Effectively use configuration statements, conditional
generates, and scripts to build variations on VHDL themes.
▪ Lab 6: Implementing Fixed and Floating Point Numbers – Construct a simple fixed point math
example and compare to the IEEE_PROPOSED fixed and floating point models.
▪ Lab 1: Flexible Functions – Construct and use predefined attributes to build functions and
procedures that automatically adjust to the size of the passed arguments as well as creating a
reusable module with unconstrained ports.
▪ Lab 2: Linked Lists with Access Types – Create linked lists to capture arbitrarily large data
sets. Also included in this lab is a reusable helper package for managing singly linked lists.
▪ Lab 3: TextIO Techniques – Load memory for synthesis via a text file using the TextIO extensions
for std_logic and std_logic_vector as provided by the std_logic_TextIO package.
▪ Lab 4: Creating Real-World Simulations – Create
spread-spectrum clocks with jitter and other real-world factors.
Model board and behavioral component delay.
▪ Lab 5: Supporting Multiple Platforms – Effectively use configuration statements, conditional
generates, and scripts to build variations on VHDL themes.
▪ Lab 6: Implementing Fixed and Floating Point Numbers – Construct a simple fixed point math
example and compare to the IEEE_PROPOSED fixed and floating point models.
