Comprehensive RFSoC-MPSoC Design Techniques

Course Description

This custom class combines essential elements of both RFSoC and MPSoC design techniques. This curriculum is based on specific areas of interest expressed by General Dynamics personnel.  Beyond the wide range of individual topics presented, the class is also a practical workshop that demonstrates key concepts.  Each attendee should plan to be fully engaged throughout, with individual questions and inquiries.  

The course covers topics pertinent to Hardware Designers,

Software Engineers and System Architects. 

  
After completing this comprehensive training, you will have the necessary skills to:

• Describe the architectural resources of the RFSoC platform, including DACs, ADCs and ZUP+ Processor System
• Understand the underlying MPSoC core functionality.
• Use the Vivado DS to create a custom platform
• Navigate the Vitis tools for software and application development and deployment
• Troubleshoot boot and configuration issues
  
  
  

Course Outline

Day 1

• RFSoC Overview
• RFSoC Hardware Overview
• RF Data Converter Solutions Overview
• Data Converter and SD-FEC Driver Overview – 10 min. + demo
• Tool Support
• RF-ADC Hardware
• Architecture
  
  
• Creating an ADC System in IP Integrator – 5 min. + demo 20 min. + lab 20 min.
• Interfaces –
• Functionality
• IP Configuration
• Software Driver Overview
• RF-DAC Hardware
• Architecture
• Creating an DAC System in IP Integrator – 5 min. + demo 20 min. + lab 20 min.
• Interfaces
• Functionality
• IP Configuration – 10 min. + lab 30 min.
• Software Driver Overview
  
  

Day 2

• Data Converter Design
• Common Features
• Design Flow
• Example Design
• Simulation – 10 min.- lab RF-ADC or RF-DAC 20 min.
• Implementation – 5 min. + lab 40 min
• Zynq UltraScale+ MPSoC Application Processing Unit
• Overview
• Cortex-A53 Processor
• Architecture Extensions
• 64-bit Architecture Features
• Exception Handling
• Cache Coherency
  
  

Day 3

• Zynq UltraScale+ MPSoC Real-Time Processing Unit
• Introduction
• L1 Cache and TCM
• Clocking, Power and Reset
• TCM Architecture
• QEMU
• Introduction
• Application Development and Debugging
• Zynq UltraScale+ MPSoC Booting
• Boot and Configuration
• Boot Image
• First Stage Boot Loader
• Introduction
• Zynq UltraScale+ MPSoC System Protection
• System Memory Management Unit
• Peripheral Protection Unit
• Memory Protection Unit
  
  
  
  
• Zynq UltraScale+ MPSoC Clocks and Resets
• Clocking
• PS Resets
• AXI
• Introduction
• Variations
• Transactions
• Zynq UltraScale+ MPSoC PMU
• Introduction
• Hardware Architecture
• PMU and the IPIs