Designing FPGAs Using the Vivado Design Suite 1 | Woodland Hills, CA

This course offers introductory training on the Vivado® Design Suite and demonstrates the FPGA design flow for those uninitiated to FPGA design.

The course provides experience with:

• Creating a Vivado Design Suite project with source files
• Simulating a design
• Performing pin assignments
• Applying basic timing constraints
• Synthesizing and implementing
• Debugging a design
• Generating and downloading a bitstream onto a demo board

What's New for 2019.1

• Vivado Design Suite Project Based Flow: Dashboard support details added
• Introduction to Vivado Reports: New information on slack histogram added

 ** This course focuses on the UltraScale architecture. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

After completing this comprehensive training, you will have the necessary skills to:

• Use the New Project Wizard to create a new Vivado IDE project
• Describe the supported design flows of the Vivado IDE
• Generate a DRC report to detect and fix design issues early in the flow
• Use the Vivado IDE I/O Planning layout to perform pin assignments
• Synthesize and implement the HDL design
• Apply clock and I/O timing constraints and perform timing analysis
• Describe the "baselining" process to gain timing closure on a design
• Use the Schematic and Hierarchy viewers to analyze and cross-probe a design
• Use the Vivado logic analyzer and debug cores to debug a design

Course Outline

Day 1

• Introduction to FPGA Architecture, 3D ICs, SoCs

Overview of FPGA architecture, SSI technology, and SoC device architecture. {Lecture}

• UltraFast Design Methodology: Board and Device Planning

Introduces the methodology guidelines covered in this course and the UltraFast Design Methodology checklist. {Lecture, Demo}

• HDL Coding Techniques

Covers basic digital coding guidelines used in an FPGA design. {Lecture}

• Introduction to Vivado Design Flows

Introduces the Vivado design flows: the project flow and non-project batch flow. {Lecture}

• Vivado Design Suite Project-based Flow

Introduces the project-based flow in the Vivado Design Suite: creating a project, adding files to the project, exploring the Vivado IDE, and simulating the design. {Lecture, Lab}

• Behavioral Simulation

Describes the process of behavioral simulation and the simulation options available in the Vivado® IDE. {Lecture}

• Vivado Synthesis and Implementation

Create timing constraints according to the design scenario and synthesize and implement the design. Optionally, generate and download the bitstream to the demo board. {Lecture, Lab}

• Basic Design Analysis in the Vivado IDE

Use the various design analysis features in the Vivado Design Suite. {Lab, Demo}

• Vivado Design Rule Checks

Run a DRC report on the elaborated design to detect design issues early in the flow. Fix the DRC violations. {Lab}

• Vivado Design Suite I/O Pin Planning

Use the I/O Pin Planning layout to perform pin assignments in a design. {Lecture, Lab}

• Vivado IP Flow

Customize IP, instantiate IP, and verify the hierarchy of your design IP. {Lecture, Lab, Demo}

Day 2

• Introduction to Clock Constraints

Apply clock constraints and perform timing analysis. {Lecture, Lab, Demo}

• Generated Clocks

Use the report clock networks report to determine if there are any generated clocks in a design. {Lecture, Demo}

• I/O Constraints and Virtual Clocks

Apply I/O constraints and perform timing analysis. {Lecture, Lab}

• Timing Constraints Wizard

Use the Timing Constraints Wizard to apply missing timing constraints in a design. {Lecture, Lab}

• Introduction to Vivado Reports

Generate and use Vivado timing reports to analyze failed timing paths. {Lecture, Demo}

• Setup and Hold Timing Analysis

Understand setup and hold timing analysis. {Lecture}

• Xilinx Power Estimator Spreadsheet

Estimate the amount of resources and default activity rates for a design and evaluate the estimated power calculated by XPE. {Lecture, Lab}

• Introduction to FPGA Configuration

Describes how FPGAs can be configured. {Lecture}

• Introduction to the Vivado Logic Analyzer

Overview of the Vivado logic analyzer for debugging a design. {Lecture, Demo}

• Introduction to Triggering

Introduces the trigger capabilities of the Vivado logic analyzer. {Lecture}

• Debug Cores

Understand how the debug hub core is used to connect debug cores in a design. {Lecture}

• Introduction to the Tcl Environment

Introduces Tcl (tool command language). {Lecture, Lab}

• Using Tcl Commands in the Vivado Design Suite Project Flow

Explains what Tcl commands are executed in a Vivado Design Suite project flow. {Lecture, Demo}

• Tcl Syntax and Structure

Understand the Tcl syntax and structure. {Lecture}