Technically Speaking, Inc
Designing FPGAs Using the Vivado Design Suite 2 | Online (Vivado 2021.1)
Course Description
This course used Vivado 2019.2 and shows you how to to build an effective FPGA design using synchronous design techniques, using the Vivado® IP integrator to create a sub-system, using proper HDL coding techniques to improve design performance, and debugging a design with multiple clock domains.
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UltraFast Design Methodology Introduction {Lecture}
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Scripting in Vivado Design Suite Project Mode {Lecture, Lab}
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Clocking Resources {Lecture, Lab}
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Synchronous Design Techniques {Lecture}
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Register Duplication {Lecture}
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Resets {Lecture, Lab}
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I/O Logic Resources {Lecture}
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Timing Summary Report {Lecture, Demo}
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Introduction to Timing Exceptions {Lecture, Lab, Demo}
Generated Clocks {Lecture, Demo}
Clock Group Constraints {Lecture, Demo}
Day 2
- Creating and Packaging Custom IP {Lecture, Lab}
- Using an IP Container {Lecture, Demo}
- Designing with IP Integrator {Lecture, Lab, Demo}
- Introduction to the HLx Design Flow {Lecture, Lab, Demo}
- Configuration Process {Lecture}
- Sampling and Capturing Data in Multiple Clock Domains {Lecture, Lab}
- Design Analysis Using Tcl Commands {Lecture, Demo, Lab}
- Power Analysis and Optimization Using the Vivado Design Suite {Lecture, Lab}
Topic Descriptions
Day 1
ô?±Œ UltraFast Design Methodology Introduction – Overview of the methodology guidelines covered in this course.
ô?±Œ Scripting in Vivado Design Suite Project Mode – Explains how to write Tcl commands in the project-based flow for a design.
ô?±Œ Clocking Resources – Describes various clock resources, clocking layout, and routing in a design.
ô?±Œ Synchronous Design Techniques – Introduces synchronous design techniques used in an FPGA design.
ô?±Œ Register Duplication – Use register duplication to reduce high fanout nets in a design.
ô?±Œ Resets – Investigates the impact of using asynchronous resets in a design.
ô?±Œ I/O Logic Resources – Overview of I/O resources and the IOB property for timing closure.
ô?±Œ Timing Summary Report – Use the post-implementation timing summary report to sign-off criteria for timing closure.
ô?±Œ Introduction to Timing Exceptions – Introduces timing exception constraints and applying them to fine tune design timing.
ô?±Œ Generated Clocks – Use the report clock networks report to determine if there are any generated clocks in a design.
ô?±Œ Clock Group Constraints – Apply clock group constraints for asynchronous clock domains.
Day 2
ô?±Œ Creating and Packaging Custom IP – Create your own IP and package and include it in the Vivado IP catalog.
ô?±Œ Using an IP Container – Use a core container file as a single file representation for an IP.
ô?±Œ Designing with IP Integrator – Use the Vivado IP integrator to create the uart_led subsystem.
ô?±Œ Introduction to the HLx Design Flow – Use the HLx design flow to increase productivity and reduce run time when designing and verifying a design.
ô?±Œ Configuration Process – Understand the FPGA configuration process, such as device power up, CRC check, etc.
ô?±Œ Sampling and Capturing Data in Multiple Clock Domains – Overview of debugging a design with multiple clock domains that require multiple ILAs.
ô?±Œ Design Analysis Using Tcl Commands – Analyze a design using Tcl commands.
ô?±Œ Power Analysis and Optimization Using the Vivado Design Suite – Use report power commands to estimate power consumption.
