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Technically Speaking, Inc - Patricia Townsend Culverson, Patricia Townsend, Technically Speaking Inc

Technically Speaking, Inc

Designing FPGAs Using the Vivado Design Suite 2 | Online & Onsite - Los Angeles CA


Please note:  This course is scheduled to run Onsite and Online simultaneously. If there is not adequate enrollment for Onsite, it may run in the Online version only.

Onsite and Online versions of this course have the exact same material and content.

After completing this comprehensive training, you will have the necessary skills to:

  • Identify synchronous design techniques
  • Build resets into your system for optimum reliability and design speed
  • Create a Tcl script to create a project, add sources, and implement a design
  • Describe and use the clock resources in a design
  • Create and package your own IP and add to the Vivado IP catalog to reuse
  • Use the Vivado IP integrator to create a block design
  • Apply timing exception constraints in a design as part of the Baselining procedure to fine tune the design
  • Describe how power analysis and optimization is performed
  • Describe the HDL instantiation flow of the Vivado logic analyzer


Course Outline

Day 1

  • UltraFast Design Methodology: Design Creation

Overview of the methodology guidelines covered in this course. {Lecture}

  • Synchronous Design Techniques

Introduces synchronous design techniques used in an FPGA design. {Lecture}

  • Resets

Investigates the impact of using asynchronous resets in a design. {Lecture, Lab}

  • Register Duplication

Use register duplication to reduce high fanout nets in a design. {Lecture}

  • Scripting in Vivado Design Suite Project Mode

Explains how to write Tcl commands in the project-based flow for a design. {Lecture, Lab}

  • Clocking Resources

Describes various clock resources, clocking layout, and routing in a design. {Lectures, Lab}

  • I/O Logic Resources

Overview of I/O resources and the IOB property for timing closure. {Lectures}

  • Creating and Packaging Custom IP

Create your own IP and package and include it in the Vivado IP catalog. {Lecture, Lab}

Day 2

  • Using an IP Container

Use a core container file as a single file representation for an IP. {Lecture, Demo}

  • Designing with the IP Integrator

Use the Vivado IP integrator to create the uart_led subsystem. {Lecture, Demo, Lab, Case Study}

  • Timing Constraints Editor

Introduces the timing constraints editor tool to create timing constraints. {Lecture}

  • Report Clock Networks

Use report clock networks to view the primary and generated clocks in a design. {Lecture, Demo}

  • Timing Summary Report

Use the post-implementation timing summary report to sign-off criteria for timing closure. {Lecture, Demo}

  • Clock Group Constraints

Apply clock group constraints for asynchronous clock domains. {Lecture, Demo}

  • Introduction to Timing Exceptions

Introduces timing exception constraints and applying them to fine tune design timing. {Lecture, Demo, Lab}

  • Power Analysis and Optimization Using the Vivado Design Suite

Use report power commands to estimate power consumption. {Lecture, Lab}

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