Welcome To Technically Speaking, Inc
Cart 0
Technically Speaking, Inc - Patricia Townsend Culverson, Patricia Townsend, Technically Speaking Inc

Technically Speaking, Inc

Designing FPGAs Using the Vivado Design Suite 3 | Online

Loading...
$1,400.00

Course Description

This course demonstrates timing closure techniques, such as baselining, pipelining, synchronization circuits, and optimum HDL coding techniques that help with design timing closure. This course also shows you how to debug your design using advanced capabilities of the Vivado® logic analyzer.

Course Outline
Day 1
    • UltraFast Design Methodology Introduction {Lecture, Demo}

    • Timing Simulation {Lecture, Lab}

    • Vivado Design Suite Non-Project Mode {Lecture}

    • Revision Control Systems in the Vivado Design Suite {Lecture, Lab}

    • Baselining {Lecture, Lab, Demo}

    • Pipelining {Lecture, Lab}

    • Inference {Lecture, Lab}

    • Synchronization Circuits {Lecture, Demo}

    Day 2

    • Report Datasheet {Lecture, Demo}
    • Report Clock Interaction {Lecture, Demo}
    • Configuration Modes {Lecture}
    • Dynamic Power Estimation Using Vivado Report Power {Lecture, Lab}
    • Debug Flow in an IP Integrator Block Design {Lecture, Lab}
    • Remote Debugging Using the Vivado Logic Analyzer {Lecture, Lab}
    • JTAG to AXI Master Core {Lecture, Demo}
    • Trigger Using the Trigger State Machine in the Vivado Logic Analyzer {Lecture, Lab}
    • Manipulating Design Properties Using Tcl {Lecture, Lab}

    Topic Descriptions

    Day 1

    ô?±Œ UltraFast Design Methodology Introduction – Introduces the methodology guidelines covered in this course.

    ô?±Œ Timing Simulation – Simulate the design post-implementation to verify that a design works properly on hardware.

    ô?±Œ Vivado Design Suite Non-Project Mode – Create a design in the Vivado Design Suite non-project mode.

    ô?±Œ Revision Control Systems in the Vivado Design Suite – Use version control systems with Vivado design flows.

    ô?±Œ Baselining – Use Xilinx-recommended baselining procedures to progressively meet timing closure.

    ô?±Œ Pipelining – Use pipelining to improve design performance.
    ô?±Œ Inference – Infer Xilinx dedicated hardware resources by writing

    appropriate HDL code.

    ô?±Œ Synchronization Circuits – Use synchronization circuits for clock domain crossings.

    Day 2

    ô?±Œ Report Datasheet – Use the datasheet report to find the optimal setup and hold margin for an I/O interface.

    ô?±Œ Report Clock Interaction – Use the clock interaction report to identify interactions between clock domains.

    ô?±Œ Configuration Modes – Understand various configuration modes and select the suitable mode for a design.

    ô?±Œ Dynamic Power Estimation Using Vivado Report Power – Use an SAIF (switching activity interface format) file to determine accurate power consumption for a design.

    ô?±Œ Debug Flow in an IP Integrator Block Design – Insert the debug cores into IP integrator block designs.

    ô?±Œ Remote Debugging Using the Vivado Logic Analyzer – Use the Vivado logic analyzer to configure an FPGA, set up triggering, and view the sampled data from a remote location.

    ô?±Œ JTAG to AXI Master Core – Use this debug core to write/read data to/from a peripheral connected to an AXI interface in a system that is running in hardware.

    ô?±Œ Trigger Using the Trigger State Machine in the Vivado Logic Analyzer – Use trigger state machine code to trigger the ILA and capture data in the Vivado logic analyzer.

    ô?±Œ Manipulating Design Properties Using Tcl – Query your design and make pin assignments by using various Tcl commands.



        Share this Product


        More from this collection

        Recently Viewed Items