Welcome To Technically Speaking, Inc
Cart 0
Technically Speaking, Inc - Patricia Townsend Culverson, Patricia Townsend, Technically Speaking Inc

Technically Speaking, Inc

Designing FPGAs Using the Vivado Design Suite 3 | Online & Onsite - Seattle WA

Loading...
$1,400.00

Please note:  This course is scheduled to run Onsite and Online simultaneously. If there is not adequate enrollment for Onsite, it may run in the Online version only.

Onsite and Online versions of this course have the exact same material and content.

Course Description

This course demonstrates timing closure techniques, such as baselining, pipelining, synchronization circuits, and optimum HDL coding techniques that help with design timing closure. This course also shows you how to debug your design using advanced capabilities of the Vivado® logic analyzer.

Course Outline
Day 1
  • UltraFast Design Methodology Introduction {Lecture}
  • Timing Simulation {Lecture, Lab}
  • Vivado Design Suite Non-Project Mode {Lecture}
  • Revision Control Systems in the Vivado Design Suite {Lecture, Lab}
  • Baselining {Lecture, Lab, Demo}
  • Pipelining {Lecture, Lab}
  • Inference {Lecture, Lab}
  • Report Clock Interaction {Lecture, Demo}

Day 2

  • Synchronization Circuits {Lecture, Demo}
  • Report Datasheet {Lecture, Demo}
  • Configuration Modes {Lecture}
  • Dynamic Power Estimation Using Vivado Report Power {Lecture, Lab}
  • Debug Flow in an IP Integrator Block Design {Lecture, Lab}
  • Remote Debugging Using the Vivado Logic Analyzer {Lecture, Lab}
  • JTAG to AXI Master Core {Lecture, Demo}
  • Trigger Using the Trigger State Machine in the Vivado Logic Analyzer {Lecture, Lab}
  • Manipulating Design Properties Using Tcl {Lecture, Lab}

Topic Descriptions

Day 1

  • UltraFast Design Methodology Introduction – Introduces the methodology guidelines covered in this course.
  • Timing Simulation – Simulate the design post-implementation to verify that a design works properly on hardware.
  • Vivado Design Suite Non-Project Mode – Create a design in the Vivado Design Suite non-project mode.
  • Revision Control Systems in the Vivado Design Suite – Use version control systems with Vivado design flows.
  • Baselining – Use Xilinx-recommended baselining procedures to progressively meet timing closure.
  • Pipelining – Use pipelining to improve design performance.
  • Inference – Infer Xilinx dedicated hardware resources by writing appropriate HDL code.
  • Report Clock Interaction – Use the clock interaction report to identify interactions between clock domains.

Day 2

  • Synchronization Circuits – Use synchronization circuits for clock domain crossings.
  • Report Datasheet – Use the datasheet report to find the optimal setup and hold margin for an I/O interface.
  • Configuration Modes – Understand various configuration modes and select the suitable mode for a design.
  • Dynamic Power Estimation Using Vivado Report Power – Use an SAIF (switching activity interface format) file to determine accurate power consumption for a design.
  • Debug Flow in an IP Integrator Block Design – Insert the debug cores into IP integrator block designs.
  • Remote Debugging Using the Vivado Logic Analyzer – Use the Vivado logic analyzer to configure an FPGA, set up triggering, and view the sampled data from a remote location.
  • JTAG to AXI Master Core – Use this debug core to write/read data to/from a peripheral connected to an AXI interface in a system that is running in hardware.
  • Trigger Using the Trigger State Machine in the Vivado Logic Analyzer – Use trigger state machine code to trigger the ILA and capture data in the Vivado logic analyzer.
  • Manipulating Design Properties Using Tcl – Query your design and make pin assignments by using various Tcl commands.

After completing this comprehensive training, you will have the necessary skills to:

  • Employ good alternative design practices to improve design reliability
  • Define a properly constrained design
  • Apply baseline constraints to determine if internal timing paths meet design timing objectives
  • Optimize HDL code to maximize the FPGA resources that are inferred and meet performance goals
  • Build a more reliable design that is less vulnerable to metastability problems and requires less design debugging later in the development cycle
  • Increase performance by utilizing FPGA design techniques
  • Use Vivado Design Suite reports and utilities to full advantage, especially the Clock Interaction report

 



      Share this Product


      More from this collection

      Recently Viewed Items