Technically Speaking, Inc
Designing FPGAs Using the Vivado Design Suite 4 | Online & Onsite-New Mexico
Please note: This course is scheduled to run Onsite and Online simultaneously. If there is not adequate enrollment for Onsite, it may run in the Online version only.
Onsite and Online versions of this course have the exact same material and content.
Course Description
This course tackles the most sophisticated aspects of the Vivado® Design Suite and Xilinx hardware. This course enables you to use the advanced capabilities of the Vivado Design Suite to achieve design closure.
Course Outline
Day 1
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UltraFast Design Methodology Introduction {Lecture}
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Scripting in Vivado Design Suite Non-Project Mode {Lecture, Lab}
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Using Procedures and Lists in Tcl Scripting {Lecture}
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Using regexp in Tcl Scripting {Lecture, Lab}
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Introduction to the Xilinx Tcl Store {Lecture, Demo}
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Debugging and Error Management in Tcl Scripting {Lecture}
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I/O Timing Scenarios {Lecture}
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Source-Synchronous I/O Timing {Lecture, Lab}
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System-Synchronous I/O Timing {Lecture, Demo}
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Timing Constraints Priority {Lecture}
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Case Analysis {Lecture}
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Daisy Chains and Gangs in Configuration {Lecture}
- � Managing Remote IP {Lecture, Lab}
- Introduction to Floorplanning {Lecture}
- Design Analysis and Floorplanning {Lecture, Lab}
- Incremental Compile Flow {Lecture, Lab}
- Re-entrant Implementation Mode {Lecture, Lab}
- Physical Optimization {Lecture, Lab}
- Vivado Design Suite ECO Flow {Lecture, Lab}
- Trigger and Debug at Device Startup {Lecture, Demo} � Scripting for a VLA Design {Lecture, Lab}
- Vivado Design Suite Debug Methodology {Lecture}
- Power Management Techniques {Lecture}
- Bitstream Security {Lecture, Lab}
Topic Descriptions
Day 1
- UltraFast Design Methodology Introduction – Introduces the UltraFastTM design methodology guidelines covered in this course.
- Scripting in Vivado Design Suite Non-Project Mode – Write Tcl commands in the non-project batch flow for a design.
- Using Procedures and Lists in Tcl Scripting – Employ procedures and lists in Tcl scripting.
- Using regexp in Tcl Scripting – Use regular expressions to find a pattern in a text file while scripting an action in the Vivado Design Suite.
- Introduction to the Xilinx Tcl Store – Introduces the Xilinx Tcl Store.
- Debugging and Error Management in Tcl Scripting - Understand how
- to debug errors in a Tcl script.
- I/O Timing Scenarios – Overview of various I/O timing scenarios, such as source- and system-synchronous, direct/MMCM capture, and edge/center aligned data.
- Source-Synchronous I/O Timing – Apply I/O delay constraints and perform static timing analysis for a source-synchronous, double data rate (DDR) interface.
- System-Synchronous I/O Timing – Apply I/O delay constraints and perform static timing analysis for a system-synchronous input interface.
- Timing Constraints Priority – Identify the priority of timing constraints. ô?±Œ Case Analysis – Understand how to analyze timing when using
- multiplexed clocks in a design.
- Daisy Chains and Gangs in Configuration – Introduces advanced configuration schemes for multiple FPGAs.
- Managing Remote IP – Store IP and related files remote to the current working project directory.
Day 2
- Introduction to Floorplanning – Introduction to floorplanning and how to use Pblocks while floorplanning.
- Design Analysis and Floorplanning – Explore the pre- and post- implementation design analysis features of the Vivado IDE.
- Incremental Compile Flow – Utilize the incremental compile flow when making last-minute RTL changes.
- Re-entrant Implementation Mode – Use re-entrant mode on partial routed nets.
- Physical Optimization – Use physical optimization techniques for timing closure.
- Vivado Design Suite ECO Flow – Use ECO flow to make changes to a previously implemented design and apply changes to the original design.
