Designing FPGAs Using Vivado JUMPSTART | Online & San Diego, CA

This is a streamlined version of the "Designing FPGAs with the Vivado Design Suite Level 1" and Designing FPGAs with the Vivado Design Suite Level 2" courses.  This 3-Day course is more cost effective and time efficient than the two separate 2-Day courses.  All topics from both courses are still covered.

Please note:  This course is scheduled to run Onsite and Online simultaneously.

Course Description

This course covers key concepts for Xilinx FPGA design using the Vivado Design Suite. It helps you to understand the critical aspects and the nuances of successful FPGA design.

For those relatively new or uninitiated to FPGA design, this course shows everything you need to get started.  That includes creating a Vivado Design Suite project with source files, simulating the design, performing pin assignments, applying comprehensive timing constraints, synthesizing, implementing, and debugging the design. Finally, the process for generating and downloading bitstream on a demo board is also covered.

After completing this comprehensive training, you will have the necessary skills to:

• Use the New Project Wizard to create a new Vivado IDE project
• Describe the supported design flows of the Vivado IDE
• Identify synchronous design techniques
• Build resets into your system for optimum reliability and design speed
• Create a Tcl script to create a project and implement a design
• Describe and use the clock resources in a design
• Create and package your own IP and add to the Vivado IP catalog
• Use the Vivado IP integrator to create a block design
• Apply timing exception constraints in a design as part of the Baselining procedure to fine tune the design
• Describe how power analysis and optimization is performed
• Describe the HDL instantiation flow of the Vivado logic analyzer
• Generate a DRC report to detect and fix design issues earlier
• Use the Vivado IDE I/O Planning layout to perform pin assignments
• Apply clock and I/O timing constraints and perform timing analysis
• Describe the "baselining" process to gain timing closure on a design
• Use the Schematic and Hierarchy viewers to analyze and cross-probe a design
• Use the Vivado logic analyzer and debug cores to debug a design

Course Outline

Day 1

• Introduction to FPGA Architecture, 3D IC, SoC {Lecture}
• HDL Coding Techniques {Lecture}
• Introduction to Vivado Design Flows {Lecture}
• Vivado Design Suite Project Mode {Lectures, Lab}
• Behavioral Simulation {Lecture}
• Synthesis and Implementation {Lecture, Lab}
• Basic Design Analysis in the Vivado IDE {Lab, Demo}
• Vivado Design Rule Checks {Lab}
• Vivado Design Suite I/O Pin Planning {Lecture, Lab}
• Synchronous Design Techniques {Lecture}
• Resets {Lecture, Lab}
• Scripting in Vivado Design Suite Project Mode {Lecture, Lab}
• Clocking Resources {Lectures, Lab}
• I/O Logic Resources {Lectures} 

Day 2

• Introduction to Clock Constraints {Lecture, Lab, Demo}
• Generated Clocks {Lecture, Demo}
• I/O Constraints and Virtual Clocks {Lecture, Lab}
• Timing Constraints Wizard {Lecture, Lab}
• Introduction to Vivado Reports {Lecture, Demo}
• Setup and Hold Timing Analysis {Lecture}
• Xilinx Power Estimator Spreadsheet {Lecture, Lab}
• Introduction to FPGA Configuration {Lecture}
• Introduction to the Vivado Logic Analyzer {Lecture, Demo}
• Introduction to Triggering {Lecture}
• Debug Cores {Lecture}
• Introduction to the Tcl Environment {Lecture, Lab}
• Using Tcl Commands in the Vivado Design Suite Project Flow {Lecture, Demo} 

Day 3

• Using an IP Container
• Designing with the IP Integrator {Lecture, Lab, Demo, Case Study}
• Timing Constraints Editor {Lecture}
• Report Clock Networks {Lecture, Demo}
• Timing Summary Report {Lecture, Demo}
• Clock Group Constraints {Lecture, Demo}
• Introduction to Timing Exceptions {Lecture, Lab, Demo}
• Power Analysis and Optimization Using the Vivado Design Suite {Lecture, Lab}
• Configuration Process {Lecture}
• HDL Instantiation Debug Probing Flow {Lecture, Lab}
• Design Analysis Using Tcl Commands {Lecture, Demo, Lab}