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Technically Speaking, Inc - Patricia Townsend Culverson, Patricia Townsend, Technically Speaking Inc

Technically Speaking, Inc

Designing with Multi-Gigabit Serial I/O | San Diego, CA - 2-Day


Course Description

Learn how to employ serial transceivers in your 7 series FPGA design. Understand and utilize the features of the serial transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection. Additional topics include use of the 7 Series FPGAs Transceiver Wizard, synthesis and implementation considerations, board design as it relates to the transceivers, and test and debugging. This course combines lectures with practical hands-on labs.

Course Outline

Day 1
▪ 7 Series FPGAs Overview
▪ 7 Series FPGAs Transceivers Overview
▪ 7 Series FPGAs Transceivers Clocking and Resets
▪ 8B/10B Encoder and Decoder
▪ Lab 1: 8B/10B Encoding and Bypass
▪ Commas and Deserializer Alignment
▪ Lab 2: Commas and Data Alignment
▪ RX Elastic Buffer and Clock Correction
▪ Lab 3: Clock Correction

▪ Channel Bonding
▪ Lab 4: Channel Bonding
  Transceiver Wizard Overview
▪ Lab 5: Transceiver Core Generatio
▪ Transceiver Implementation
▪ Physical Media attachment
▪ 64B/66B Encoding and the Gearbox
▪ Lab 6: 64B/66B Encoding
▪ Transceiver Test and Debugging
▪ Lab 7: Transceiver Debugging
▪ Lab 8: IBERT Lab
    Lab Descriptions
    ▪ Lab 1: 8B/10B Encoder and Decoder – Utilize the 8B/10B encoder and decoder and observe running disparity. Learn how to bypass the 8B/10B encoder and decoder.
    ▪ Lab 2: Commas and Data Alignment – Use programmable comma detection to align a serial data stream.
    ▪ Lab 3: Clock Correction – Utilize the attributes and ports associated with clock correction to compensate for frequency differences in the TX and RX clocks.
    ▪ Lab 4: Channel Bonding – Modify a design to use two transceivers bonded together to form one virtual channel.
    ▪ Lab 5: Transceiver Core Generation – Use the 7 Series FPGAs Transceivers Wizard to create instantiation templates.
    ▪ Lab 6: 64B/66B Encoding – Generate a 64B/66B transceiver core by using the 7 Series FPGAs Transceivers Wizard, simulate the design,and analyze the results.
    ▪ Lab 7: Debug the transceiver IP using the
    IP example design and Vivado debug cores.
    ▪ Lab 8: IBERT – Create an IBERT design to verify physical links


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