Technically Speaking, Inc
DSP Design Using System Generator & Model Composer | Online
After completing this comprehensive training, you will have the necessary skills to:
- Describe the advantages of using FPGAs over traditional processors for DSP designs
- Describe the System Generator design flow for implementing RTL based FPGA based DSP functions.
- Describe the Model Composer design flow for implementing C/C++ based FPGA based DSP functions in conjunction with Vivado HLS
- Utilize fixed point binary arithmetic and identify how to use this knowledge to create efficient designs in FPGAs
- Recognize how both the CLB slices in FPGAs and the more advanced DSP48s are used to implement DSP algorithms
- Run Hardware Co-simulation
- Explain the dataflow through the device and how to use distributed memory, block RAM, registers, and SRLs to properly implement these designs
- Construct different FIR filter and FFT implementations and how to optimize these implementations in the FPGA
- Design a processor controllable interface using System Generator
- Overview, using FPGAs for DSP functions
- Implementing Filter in FPGA Fabric
- Introduction to System Generator
- Simulink Software Basics
- Lab 1: Using the Simulink Software
- Basic Xilinx Design Capture
- Demo: System Generator Gateway Blocks
- Lab 2: Getting Started with Xilinx System Generator
- Signal Routing
- Lab 3: Signal Routing
- Implementing System Control
- Lab 4: Implementing System Control
- Multi-Rate Systems
- Lab 5: Designing a MAC-Based FIR
- Filter Design
- Lab 6: Designing a FIR Filter Using the FIR Compiler Block
- System Generator, Vivado Design Suite, and Vivado HLS Integration
- Lab 7: System Generator and Vivado IDE Integration
- DSP Platforms
- Lab 8: System Generator and Vivado HLS Tool Integration
- Lab 9: AXI4-Lite Interface Synthesis
- Introduction to Model Composer
- Demo: Introduction to Model Composer
- Importing C/C++ Code to Model Composer
- Automatic Code Generation Using Model Composer
- Lab 10: Model Composer and Vivado IDE Integration
- Utilizing Xilinx IP tools for FIR/FFT/DDS, etc.
- Lab 1: Using the Simulink Software – Learn how to use the toolbox blocks in the Simulink software and design a system. Understand the effect sampling rate.
- Lab 2: Getting Started with Xilinx System Generator – Illustrates a DSP48-based design. Perform hardware co-simulation verification targeting a Xilinx evaluation board.
- Lab 3: Signal Routing – Design padding and unpadding logic by using signal routing blocks.
- Lab 4: Implementing System Control – Design an address generator circuit by using blocks and Mcode.
- Lab 5: Designing a MAC-Based FIR – Using a bottom-up approach, design a MAC-based bandpass FIR filter and verify through hardware co-simulation by using a Xilinx evaluation board.
- Lab 6: Designing a FIR Filter Using the FIR Compiler Block – Design a bandpass FIR filter by using the FIR Compiler block to demonstrate increased productivity. Verify the design through hardware co-simulation by using a Xilinx evaluation board.
- Lab 7: System Generator and Vivado IDE Integration – Embed System Generator models into the Vivado IDE.
- Lab 8: System Generator and Vivado HLS Tool Integration – Generate IP from a C-based design to use with System Generator.
- Lab 9: AXI4-Lite Interface Synthesis – Package a System Generator for DSP design with an AXI4-Lite interface and integrate this packaged IP into a Zynq UltraScale+ MPSoC processor system.
- Lab 10: Model Composer and Vivado IDE Integration - Embed a Model Composer model into the Vivado IDE.