Welcome To Technically Speaking, Inc
Cart 0
Technically Speaking, Inc - Patricia Townsend Culverson, Patricia Townsend, Technically Speaking Inc

Technically Speaking, Inc

DSP Design Using System Generator | Online

Loading...
$1,400.00

Course Description

This course allows you to explore the System Generator tool and to gain the expertise you need to develop advanced, low-cost DSP designs. This intermediate course in implementing DSP functions focuses on learning how to use System Generator for DSP, design implementation tools, and hardware co-simulation verification. Through hands-on exercises, you will implement a design from algorithm concept to hardware verification using the Xilinx FPGA capabilities.

Course Outline

Day 1

  • Introduction to System Generator
  • Simulink Software Basics
  • Lab 1: Using the Simulink Software
  • Basic Xilinx Design Capture
  • Demo: System Generator Gateway Blocks
  • Lab 2: Getting Started with Xilinx System Generator
  • Signal Routing
  • Lab 3: Signal Routing
  • Implementing System Control
  • Lab 4: Implementing System Control
          Day 2
          • Multi-Rate Systems
          • Lab 5: Designing a MAC-Based FIR
          • Filter Design
          • Lab 6: Designing a FIR Filter Using the FIR Compiler Block
          • System Generator, Vivado Design Suite, and Vivado HLS Integration Lab 7: System Generator and Vivado IDE Integration
          • Kintex-7 FPGA DSP Platforms
          • Lab 8: System Generator and Vivado HLS Tool Integration
          • Lab 9:
          • AXI4-Lite Interface Synthesis

          Lab Descriptions

          • Lab 1: Using the Simulink Software Learn how to use the toolbox blocks in the Simulink software and design a system. Understand the effect sampling rate.
          • Lab 2: Getting Started with Xilinx System Generator Illustrates a DSP48-based design. Perform hardware co-simulation verification targeting a Xilinx evaluation board.
          • Lab 3: Signal Routing Design padding and unpadding logic by using signal routing blocks.
          • Lab 4: Implementing System Control Design an address generator circuit by using blocks and Mcode.
          • Lab 5: Designing a MAC-Based FIR Using a bottom-up approach, design a MAC-based bandpass FIR filter and verify through hardware co-simulation by using a Xilinx evaluation board.
          • Lab 6: Designing a FIR Filter Using the FIR Compiler Block Design a bandpass FIR filter by using the FIR Compiler block to demonstrate increased productivity. Verify the design through hardware co-simulation by using a Xilinx evaluation board.
          • Lab 7: System Generator and Vivado IDE Integration Embed System Generator models into the Vivado IDE.
          • Lab 8: System Generator and Vivado HLS Tool Integration Generate IP from a C-based design to use with System Generator.
          • Lab 9: AXI4-Lite Interface Synthesis Package a System Generator for DSP design with an AXI4-Lite interface and integrate this packaged IP into a Zynq All Programmable SoC processor system.

          * This course focuses on the 7 series architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations. The ZC702 or ZedBoard is required for the "AXI4-Lite Interface Synthesis" lab.

          After completing this comprehensive training, you will have the necessary skills to:

          • Describe the System Generator design flow for implementing functions
          • DSP
          • Identify Xilinx FPGA capabilities and how to implement a design from algorithm concept to hardware simulation

          • List various low-level and high-level functional blocks available in System Generator

          • Run hardware co-simulation

          • Identify the high-level blocks available for FIR and FFT designs

          • Implement multi-rate systems in System Generator

          • Integrate System Generator models into the Vivado IDE

          • Design a processor-controllable interface using System Generator for DSP

          • Generate IPs from C-based design sources for use in the System Generator environment


          Share this Product


          More from this collection

          Recently Viewed Items