DSP Using System Generator and FPGA Implementation Techniques | Online

Course Description

This custom course provides a foundation for using System Generator, the overall MATLAB and Simulink tools, along with essential Digital Signal Processing (DSP) techniques for Xilinx FPGAs. The course begins with a detailed discussion of FPGA resources specific to DSP design and optimization.  The body of the course explores a variety of filter techniques with emphasis on optimal implementation in Xilinx devices and continues with an examination of FIRs and FFTs.  The course introduces System Generator for modeling cost-efficient DSP Systems and exporting IP for integration using Vivado. The course is complemented by hands-on exercises to reinforce the concepts learned. 

After completing this comprehensive training, you will have the necessary skills to:

• Describe the advantages of using FPGAs over traditional processors for DSP designs
• Describe the System Generator design flow for implementing FPGA based DSP functions.
• Utilize fixed point binary arithmetic and identify how to use this knowledge to create efficient designs in FPGAs
• Recognize how both the CLB slices in FPGAs and the more advanced DSP48s are used to implement DSP algorithms
• Run Hardware Co-simulation
• Explain the dataflow through the device and how to use distributed memory, block RAM, registers, and SRLs to properly implement these designs
• Construct different FIR filter and FFT implementations and how to optimize these implementations in the FPGA
• Design a processor controllable interface using System Generator
    

Course Outline

• Back to Basics, FPGA versus Processor Implementation
• Architecture
• FPGA Math
• FIR Filter
• Exercise 1: Filter Implementation, Resource and Performance Estimation
• Fast Fourier Transform

Day 2

• Simulink Software Basics
• Basic Xilinx Design Capture
• Lab 2: Getting Started with Xilinx System Generator
• Implementing System Control
• Lab 3: Designing a FIR filter using FIR compiler block
• System Generator, Vivado DS, Vivado HLS
• Lab 4: AXI4-lite Interface Synthesis
• Lab 5: Using Model Composer

Lab Descriptions

• Lab 1: Filter Implementation, Resource and Performance Estimation – Learn how and when to use various implementation strategies for optimal filter implementation.
• Lab 2: Getting Started with Xilinx System Generator – Illustrates a DSP48-based design. Perform hardware co-simulation verification targeting a Xilinx evaluation
• Lab 3: Designing a FIR Filter Using the FIR Compiler Block – Design a bandpass FIR filter by using the FIR Compiler block to demonstrate increased productivity. Verify the design through hardware co-simulation by using a Xilinx evaluation board.

• Lab 4: AXI4-Lite Interface Synthesis – Package a System Generator for DSP design with an AXI4-Lite interface and integrate this packaged IP into a Zynq All Programmable SoC processor