Technically Speaking, Inc

Designing with Verilog and Xilinx FPGA Design w Vivado (1) | Orange County, CA

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Course Description

This custom comprehensive course is a thorough introduction to the Verilog language and the Xiliinx Vivado tools. The emphasis is on writing Register Transfer Level (RTL) and behavioral source code. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn advanced coding techniques that will increase your overall Verilog proficiency and enhance your FPGA optimization. This course covers Verilog 1995 and 2001.

After learning the basics of Verilog, you'll also learn how to apply those coding techniques to get started with optimized FPGA application development using Vivado DS 2018.x

In this three-day course, you will gain valuable hands-on experience. Incoming students with little or no Verilog knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations.

Course Outline

Day 1

Hardware Modeling Overview
Verilog Language Concepts
Modules and Ports
Demo: Multiplexer
Lab 1: Building Hierarchy
Introduction to Testbenches
Lab 2: Verilog Simulation and RTL Verification
Verilog Operators and Expressions

Continuous Assign Statements
Lab 3: Memory

Day 2

Verilog Procedural Statements
Lab 4: Clock Divider and Address Counter
Controlled Operation Statements
Lab 5: n-bit Binary Counter and RTL Verification
Verilog Tasks and Functions
Advanced Language Concepts
Finite State Machines
Lab 6: Finite State Machines
Targeting Xilinx FPGAs
Lab 7: Implement and Download
Advanced Verilog Testbenches
Lab 8: Using Verilog File I/O

Day 3

Introduction to FPGA Architecture, 3D IC, SoC
Introduction to Vivado Design Flows
Vivado Design Suite Project Mode
Basic Design Analysis in the Vivado IDE
Vivado Design Rule Checks
Vivado Design Suite I/O Pin Planning
Introduction to Clock Constraints
Generated Clocks
I/O Constraints and Virtual Clocks
Timing Constraints Wizard
Introduction to Vivado Reports
Setup and Hold Timing Analysis

Lab Descriptions

The labs for this course provide a practical foundation for creating synthesizable RTL code. All aspects of the design flow are covered in the labs. The labs are written, synthesized, behaviorally simulated, and implemented by the student. The focus of the labs is to write code that will optimally infer reliable and high-performance circuits. The labs culminate in a functional calculator that students verify in simulation.

* This course does not focus on any particular architecture. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

After completing this comprehensive training, you will have the necessary skills to:

Write RTL Verilog code for synthesis
Write Verilog test fixtures for simulation
Create a Finite State Machine (FSM) by using Verilog
Target and optimize Xilinx FPGAs by using Verilog
Use enhanced Verilog file I/O capability
Run a timing simulation by using Xilinx Simprim libraries
Create and manage designs within the Vivado Design Suite environment
Download to the evaluation demo board