Spartan-6 MIGRATION

Are you considering migrating a legacy Spartan-6® FPGA design to newer Xilinx technologies, such as Artex-7, Spartan-7, Kintex-7, Virtex-7 or UltraScale. This course supports both experienced and less experienced FPGA designers who have some familiarity with Xilinx design principles.    

Course Description

Are you considering migrating a legacy Spartan-6® FPGA design to newer Xilinx technologies, such as Artex-7, Spartan-7, Kintex-7, Virtex-7 or UltraScale. This course supports both experienced and less experienced FPGA designers who have some familiarity with Xilinx design principles.    

This course is a fast-paced, concise presentation of topics for effective migration to 7-series, UltraScale or Zynq based architectures.  To that end, the topics are presented in a side-by-side comparison manner.

Successful migration requires both device and design flow updates. Every aspect of the newer FPGA design process is covered, from HDL design entry, through implementation, to timing verification.    

The course covers key differences in the ISE and Vivado ML Edition capabilities and resources.

  

After completing this comprehensive training, you will have the necessary skills to:

• Compare the functionality of the Spartan-6 Slice, LUT and CLB resources versus newer Xilinx FPGA devices
• Leverage enhanced block RAM and DSP resources available in newer families
• Properly design for the I/O block, IDELAY, DDR and SERDES resources
• Migrate from DCM, PLL, to MMCM resources
• Identify the enhanced clock routing features in UltraScale devices
• Rewrite your UCF based constraints in XDC format
• Describe timing closure techniques in Vivado ML
• Manage Control Sets in 7-Series for optimal mapping
  
  
  
  
  

Course Outline

Day 1

• ISE versus Vivado ML Edition Flow
• Vivado ML Project Mode
• CLB Architecture in 7-Series/UltraScale
• Clocking Resources in 7-Series/UltraScale
• Lab 1: Configuring MMCM
• Using IP Integrator
• Lab 2: Using IP Integrator
• Memory Resources, LUT, BRAM and URAM
• DSP48-E Resources in 7-Series / UltraScale

Day 2

• I/O Resources in 7-Series / UltraScale
• Lab 3: Targeting I/O Resources
• UCF to XDC Constraints – Clocks & I/O (part 1)
• UCF to XDC Constraints – Path Exceptions (part 2)
• Lab 4: Writing XDC constraints
• Vivado Timing Closure Techniques
• Memory Controllers in 7-Series / UltraScale
• Package Migration and Power Management

Lab Descriptions

• Lab 1: Configuring MMCM: Use the IP catalog to create and configure MMCM. Instantiate component into design.
• Lab 2: Using IP Integrator – Using IPI to integrate IP blocks with AXI-4 interfaces.
• Lab 3: I/O Resources– Using Vivado ML, complete the construction of the transmit SERDES datapath. Explore, through simulation, the behavior of the various blocks.
• Lab 4: Writing XDC Constraints: Fully constrain simple design with synchronous logic, evaluate results in post implementation Static-Timing Analysis.