Technically Speaking, Inc
Verilog for Experienced VHDL Users | Orange County
Course Description
Are you a traditional IEEE-1076 VHDL user who must now accomplish mixed mode synthesis and simulation? This concise 1-day course is designed for hardware designers accustomed to the nuances and syntax requirements of the VHDL language and needing to perform similar operations using IEEE-1364 Verilog. Most tools today support single kernel VHDL and Verilog module usage, but are you ready and capable in either mode? This course bridges the gap by building upon your existing VHDL skills.
Course Outline
▪ Course Introduction: Verilog and VHDL Structural Overview
▪ SYNTHESIS
▪ Comparing Process and Procedural blocks
▪ Data-types and Synthesis Requirements
▪ Creating Hierarchy & Design Parametrization
▪ Lab 1:
▪ RAM & ROM Optimization
▪ FSM Coding in Verilog
▪ Lab 2:
▪ SIMULATION
▪ Basic Testbench Structure and Utilization
▪ Verilog File I/O Basic Usage
▪ Lab 3:
▪ OTHER
▪ Header Files versus Packages/Libraries
▪ Xilinx Tool Specific Verilog Usage Recommendations
