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Technically Speaking, Inc

Vitis for Versal ACAP Workshop - 2021.1


 Workshop Description

This workshop demonstrates how Vitis is used to program all the features of the Versal ACAP platform.   That includes the high performance Scalar Engines ( Arm A72 and R5F), the traditional FPGA Programmable Logic (via HLS) and the AI Engines ( via the dedicated AI Engine compiler).   Vitis supports the development and verification of each functional sub-section, and then necessary system level integration and debug.  

The emphasis of this course is on:

  • Creating Hardware Acceleration Kernels within Vitis (HLS)
  • Reviewing the basics of using the Vitis platform
  • Coding applications for A72 and R5F processor cores
  • Developing hardware kernels that target the AI Engines



    Workshop Outline

    • Vitis Project structure / Designer Productivity  
    • Using Vitis for Hardware Acceleration 
    • Overview of Embedded Software Development
    • Driving the Vitis Software Development Tool

    Introduces the basic behaviors required to drive the Vitis tool to generate a debuggable C/C++ application. {Lecture, Lab}

    • Standalone Software Platform Development and Coding Support

    Covers the various software components, or layers, supplied by Xilinx that aid in the creation of low-level software. Also the basic services (libraries) available. {Lecture, Lab}

    • Linux Software Application Development Overview

    Highlights important parts of the underlying Linux system as it pertains to applications. {Lecture, Lab}

    Reviews the use of the Vitis tool for Linux software development. {Lecture}

    • System Debugger

    Describes the basics of actually running a debugger and illustrates the most commonly used debugging commands. {Lecture, Lab}

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