Technically Speaking, Inc
Vivado for Experienced Xilinx Users
This custom class bridges the gap for existing ISE users, Moving to Vivado 2014.1 (or later). This is a comprehensive update and introduction to the most powerful and useful features of Xilinx Vivado® Design Suite. You’ll learn the underlying database and static timing analysis (STA) mechanisms.
You’ll learn to utilize Tcl for navigating the design, creating the complete range of Xilinx design timing constraints (XDC), and creating timing reports.
That includes multi-cycle paths, false path, and min/max timing constraints.
Finally, you will learn how to maximize productivity by using the Vivado Tcl scripting capabilities for both the project-based and non-project batch flows, as well as Guided Design Flows.
Course Outline and Lab Descriptions
Comparing ISE to Vivado
XST versus Vivado Synthesis
▪ Accessing the Design Database Lab 1: Vivado Database Leveraging IP Integrator
Lab 2: IP Integrator
XDC Constraints & Timing Report
UCF to XDC Conversion Lab 3: Timing Constraints