Technically Speaking, Inc
Zynq UltraScale+ MPSoC for the Hardware Designer | Online & Onsite - San Diego CA
Please note: This course is scheduled to run Onsite and Online simultaneously. If there is not adequate enrollment for Onsite, it may run in the Online version only.
Onsite and Online versions of this course have the exact same material and content.
Course Description
This one-day course is structured to provide hardware designers with an overview of many of the capabilities and support for the Zynq® UltraScale+TM MPSoC family from a hardware architectural perspective.
- Zynq UltraScale+ MPSoC Application Processing Unit {Lecture, Lab}
- Zynq UltraScale+ MPSoC HW-SW Virtualization {Lecture, Lab}
- Zynq UltraScale+ MPSoC Real-Time Processing Unit {Lecture,
- Demo, Lab}
- Introduction to QEMU {Lecture, Demo, Lab}
- Zynq UltraScale+ MPSoC Boot and Configuration {Lecture, Lab}
- Zynq UltraScale+ MPSoC System Protection {Lecture, Lab}
- Zynq UltraScale+ MPSoC Clocks and Resets {Lecture, Demo}
- Introduction to AXI {Lecture, Demo, Lab}
- Zynq UltraScale+ MPSoC PMU Hardware Perspective {Lecture, Lab}
Topic Descriptions
- Zynq UltraScale+ MPSoC Application Processing Unit – Introduction to the members of the APU, specifically the CortexTM- A53 processor and how the cluster is configured and managed.
- Zynq UltraScale+ MPSoC HW-SW Virtualization – Covers the hardware and software elements of virtualization. The lab demonstrates how hypervisors can be used.
- Zynq UltraScale+ MPSoC Real-Time Processing Unit – Introduction to the various elements within the RPU and different modes of configuration.
- Introduction to QEMU – Introduction to the Quick Emulator, which is the tool used to run software for the Zynq UltraScale+ MPSoC device when hardware is not available.
- Zynq UltraScale+ MPSoC Boot and Configuration – How to implement the embedded system, including the boot process and boot image creation.
- Zynq UltraScale+ MPSoC System Protection – Covers all the hardware elements that support the separation of software domains.
- Zynq UltraScale+ MPSoC Clocks and Resets – Overview of clocking and reset, focusing more on capabilities than specific implementations.
- Introduction to AXI – Understanding how the PS and PL connect enables designers to create more efficient systems.
- Zynq UltraScale+ MPSoC PMU Hardware Perspective – Overview of the PMU and the power-saving features of the device.
* This course focuses on the Zynq UltraScale+ MPSoC architecture. Check with your local Authorized Training Provider for the specifics of the in-class lab environment or other customizations. The 2015.4 version of this class does not use a physical board, but rather a local emulation environment and the Vivado Design Suite.
After completing this comprehensive training, you will have the necessary skills to:
-
Enumerate the key elements of the application processing unit (APU) and real-time processing unit (RPU)
-
List the various power domains and how they are controlled
-
Describe the connectivity between the processing system (PS)
and programmable logic (PL)
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Utilize QEMU to emulate hardware behavior
