Technically Speaking, Inc
Zynq UltraScale+ MPSoC for the Software Developer | Online & Onsite - San Diego, CA
Course Description
This two-day course is structured to provide system architects with an overview of the capabilities and support for the Zynq® UltraScale+TM MPSoC family.
Topic Descriptions
Day 1
▪ Zynq UltraScale+ MPSoC Overview – Overview of the Zynq UltraScale+ MPSoC device.
▪ Zynq UltraScale+ MPSoC HW-SW Virtualization – Covers the hardware and software elements of virtualization. The lab demonstrate how hypervisors can be used.
▪ Introduction to QEMU – Introduction to the Quick Emulator, which is the tool used to run software for the Zynq UltraScale+ MPSoC device when hardware is not available.
▪ Zynq UltraScale+ MPSoC Security and Software Test Library – Introduction to the purpose and API of the Software Test Library.
▪ Zynq UltraScale+ MPSoC System Protection – Covers all the hardware elements that support the separation of software domains.
▪ Zynq UltraScale+ MPSoC Security Features – Aspects that implement tamper resistance and control access to the hardware and bitstream.
Day 2
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▪ Zynq UltraScale+ MPSoC Power Management – Overview of the PMU and the power-saving features of the device.
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▪ Zynq UltraScale+ MPSoC System Coherency – Learn how information is synchronized within the API and through the ACE/AXI ports.
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▪ Zynq UltraScale+ MPSoC DDR and QoS {Lecture, Demo, Lab} – Understand how DDR can be configured to provide the best performance for your system.
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▪ Zynq UltraScale+ MPSoC Boot and Configuration – How to implement the embedded system, including the boot process and boot image creation.
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▪ Zynq UltraScale+ MPSoC Ecosystem Support – Overview of supported operating systems, software stacks, hypervisors, etc.
* This course focuses on the Zynq UltraScale+ MPSoC architecture. Check with your local Authorized Training Provider for the specifics of the in-class lab environment or other customizations. The 2015.4 version of this class does not use a physical board, but rather a local emulation environment and the Vivado Design Suite.
After completing this comprehensive training, you will have the necessary skills to:
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▪ Distinguish between asymmetric multi-processing (AMP) and symmetric multi-processing (SMP) environments
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▪ Identify situations when the ARM® TrustZone technology and/or a hypervisor should be used
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▪ Effectively use power management strategies and leverage the capabilities of the platform management unit (PMU)
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▪ Define the boot sequences appropriate to the needs of the system
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▪ Define the underlying implementation of the application processing unit (APU) and real-time processing unit (RPU) to make best use of their capabilities
